The present invention relates to an instruction processor for executing translation instructions in accordance with pipeline control.
A translation instruction is an instruction to be utilized, for example, to translate EBCDIK codes into ISO codes.
FIG. 1A depicts the instruction format of translation instructions. Bits 0-7 of the instruction constitute an operation code (to be referred to as OP code hereinafter). A length part comprises bits 8-15 and indicates the operand length of the first operand. Bits 16-19 and 20-31 represent the base register number and displacement, respectively of the first operand; while bits 32-35 and 36-47 indicate the base register number and displacement, respectively of the second operand. The first addresses of the first and second operands each is obtained by adding the displacement to the base register content.
A plurality of data items are fetched from a buffer storage (FIG. 2) to be described later by specifying a first address obtained by use of the base register and the displacement of the first operand. These fetched data items are called argument bytes which form the first operand. The address value of the second operand is added to the respective argument value of the first operand in order to obtain a plurality of data items (function bytes) from the buffer storage by specifying the results of the addition described above as the relevant addresses, thereby replacing the store positions for storing the argument bytes in the buffer storage with the function bytes.
FIG. 1B illustrates the address A.sub.1i (i=1 to L) of a plurality of argument bytes and the values of data D.sub.1i (i=1 to L) stored in the buffer storage before and after execution of a translation instruction. For instance, the address of the i-th argument byte is obtained from A.sub.1i =(B.sub.1)+D.sub.1 +i-1, whereas the values of D.sub.1i before the translation instruction execution and D.sub.1i ' thereafter are represented by D.sub.1i =OP.sub.1i and D.sub.1i '=OP.sub.2i, respectively. Notation of (B.sub.1) indicates the content (address value) of a register specified by B.sub.1.
FIG. 1C shows values obtained by adding the argument byte values OP.sub.1i (i=1 to L) to the respective second operand address values ((B.sub.2)+D.sub.2) and the values of store data (function bytes), D.sub.2i =OP.sub.2i (i=1 to L) fetched from the buffer storage by specifying the results of the addition as the fetch addresses.
FIG. 2 is a schematic block diagram illustrating the prior art instruction processor. FIG. 3 is a processing flow of instruction execution in the prior art instruction processor. Referring to FIG. 2, an instruction register 10 is in the state for holding an instruction in the format of FIG. 1A. The instruction processor of FIG. 2 further comprises selectors 20 and 21 for selecting base register numbers B1 and B2 and displacement D1 and D2. The base register number B1 and displacement D1 are selected to execute an address calculation for the first operand, while the base register number B2 and displacement D2 are selected to calculate the address of the second operand. An incrementer 11 is provided to generate a constant unit to each argument byte when the first operand address calculation is executed.
The constant unit to each argument byte is 0, 1, . . . , and (i-1) for the first, second, . . . , and i-th argument bytes, respectively. The step for the value incrementation is one in this example because data in the length of a byte is processed for each execution of the processing. A register group 12 is utilized to hold the values of base registers specified by the base register numbers B1 and B2. A selector 22 selects an incrementer 11 and a one-byte separate circuit 23 for the first and second address calculations, respectively. An adder 13 calculates a buffer storage address, while a buffer storage 15 is used to fetch and store therein a memory data item fetched by use of the address calculated by the adder 13. The buffer storage 15 can fetch a plurality of bytes at a time and can perform a data fetch operation and a data store operation at the different addresses during a cycle on a time-slice basis. The resultant value from the adder 13 is also transferred to a store address buffer 14 and is held as a store address. A signal line 50 supplies a fetch address for a data fetch operation to the buffer storage 15, while a signal line 51 supplies a write address thereto. An aligner circuit 16 aligns data fetched from the buffer storage 15. An align operation is conducted to shift the data fetched from the buffer storage 15 to a predetermined position (for example, at the left or right end). An operand buffer circuit 17 is used to store therein a fetched operand. The instruction processor of FIG. 2 further includes an operation unit 18 and a store data register 19. The one-byte separate circuit 23 receives the first operand from the operand buffer circuit 17 and holds the operand, and also separates the first operand data by one byte at a time and outputs the separated one-byte data item on the signal line 52.
The instruction processor of the prior art depicted in FIG. 2 processes translation instructions in accordance with the processing flow depicted in FIG. 3. Referring to FIG. 3, D, A, L, and E indicate instruction processing cycles in the pipeline control system. The instruction decode cycle D is utilized to decode an instruction stored in the instruction register 10 and to generate information necessary for the instruction processing, and furthermore, to perform an address calculation required to fetch a memory operand for the instruction by use of the address adder 13. In the cycle A, a memory data item is fetched from the buffer storage 15 by use of an operand address calculated in the cycle D. The fetched data item is stored in the operand buffer 17 in the cycle L. A predetermined operation by the instruction is executed in the operation unit 18 during the cycle E.
In the conventional data processing system of FIG. 2, the processing of translation instructions are carried out as follows.
First, the base register value B1 and the displacement D1 are selected by the selectors 20 and 21. The selector 22 selects the value (initially set to 0) from the incrementer 11 in order to calculate the first operand address by use of the adder 13. The address value is transferred to the buffer storage 15 to fetch the first operand; and at the same time, it is stored in the store address buffer 14 so as to be utilized as the store address for storing the second operand. A data item comprising a plurality of bytes (n bytes) can be fetched from the buffer storage 15 at a time. The first operand, which is the fetched data, is stored in the one-byte separate circuit 23 through the operand buffer 17. In the one-byte separate circuit 23 one byte of data is separated from said first operand data at a time and the separated one-byte data item is outputted to the signal line 52. Next, the selectors 20 and 21 select the base register value B2 and displacement D2, respectively, and the selector 22 selects a signal line 52 in order to execute the second operand address calculation by use of the adder 13. That is, an operation of (B2)+D2+OP.sub.11 is carried out. A byte (function byte) constituting the second operand is fetched from the buffer storage 15 based on the calculated address value and is transferred through the operand buffer 17, the operation unit 18, and the store data storage 19 and is stored in the buffer register 15. When storing the data within the store data register 19 into the buffer storage 15, the fetch address of the first operand which is held in the store address buffer 14 is used. Since at this time the first operand has been fetched by n bytes at one time, it is necessary to carry out n times of data storing for the address held in the store address buffer 14. Thus, the data storing is made such that when storing the second operand the address in the store address buffer 14 is counted up one by one to produce the address for storing, or that until n times of reading out of the second operands have been finished, the second operands to be stored are held in the store register 19, and when n bytes of the second operands have been fetched, the fetched second operands are stored at one time by using the address in the store address buffer 14.
Similarly, the bytes constituting the second operand can be fetched by sequentially separating each byte from the n-byte first operand fetched beforehand in the one-byte separate circuit 23. When the n-th fetch operation is completed, the argument bytes (n bytes) of the subsequent first operand are fetched. After this fetch operation is finished, the (n+1)th second operand fetch operation can be initiated.
FIG. 3 depicts the same operation when n=8. Referring to FIG. 3, the second operand is fetched with a two-cycle overhead elapsed after the first address calculation of the first operand. When the function bytes are successively fetched eight times and the argument bytes first fetched are completely processed, it is allowed to initiate the second operand fetch operation again when the two-cycle overhead time is elapsed after the first operand fetch operation. Consequently, two D cycles are not utilized each time the eight operations described above are completed.
In the conventional data processing system described hereabove, the same adder 13 is utilized to execute the first and second operand calculations and the same buffer storage 15 is used to fetch the argument and function bytes, hence several cycles (two cycles in FIG. 2) of the overhead time appear between the time when the first operand is fetched and the time when the second operand fetch operation is started. The overhead takes place once every n operations described above because of the restriction of the startup operation as well as that of the data width allowed for fetching data from the buffer storage 15 at a time, that of the data width of the operand buffer 17 and one-byte separate circuit 23, and the like. Frequency n is represented by the data length of data which can be stored in the operand buffer 17 and one-byte separate circuit 23 at a time under various restrictions.
In addition, n bytes of the first operand are fetched at a time and are stored in the one-byte seperate circuit 23 to minimize the overhead described above, so the one-byte separate circuit 23 is necessary which separates an associated byte from the n-byte data and transfers, the obtained byte in the address adder 13 each time the second operand address calculation is performed. Further, in the prior art device, while the first operand is read out by n bytes at one time, the storing of the second operand is carried out by every one byte, therefore, it becomes necessary to provide either an address count up circuit within the store address buffer 14 or a circuit for arranging n bytes of data in order within the store data register 19.